IEEE - Institute of Electrical and Electronics Engineers, Inc. - A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

Author(s): Liang-Ying Lu ; Ching-Yao Chang ; Zhao-Hong Chen ; Bo-Ting Yeh ; Tai-Hua Lu ; Peng-Yu Chen ; Pin-Hao Tang ; Kuen-Jong Lee ; Lih-Yih Chiou ; Soon-Jyh Chang ; Chien-Hung Tsai ; Chung-Ho Chen ; Jai-Ming Lin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: Macau, China
Conference Date: 25 January 2016
Page(s): 17 - 18
ISBN (CD): 978-1-4673-9568-7
ISBN (Electronic): 978-1-4673-9569-4
ISSN (Electronic): 2153-697X
DOI: 10.1109/ASPDAC.2016.7427980
Regular:

A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an... View More

Advertisement