IEEE - Institute of Electrical and Electronics Engineers, Inc. - 26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS

2016 IEEE International Solid-State Circuits Conference (ISSCC)

Author(s): Hidenori Okuni ; Akihide Sai ; Tuan Thanh Ta ; Satoshi Kondo ; Takashi Tokairin ; Masanori Furuta ; Tetsuro Itakura
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: San Francisco, CA, USA
Conference Date: 31 January 2016
Page(s): 436 - 437
ISBN (Electronic): 978-1-4673-9467-3
ISBN (Paper): 978-1-4673-9466-6
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2016.7418094
Regular:

Various Ultra-Low-Power (ULP) RX architectures [1-4] for Bluetooth™ Low Energy (BLE) have been developed for minimizing the RX power consumption. A PLL-based RX architecture [1] is very... View More

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