IEEE - Institute of Electrical and Electronics Engineers, Inc. - 19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS

2016 IEEE International Solid-State Circuits Conference (ISSCC)

Author(s): Junheng Zhu ; Romesh Kumar Nandwana ; Guanghua Shu ; Ahmed Elkholy ; Seong-Joong Kim ; Pavan Kumar Hanumolu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: San Francisco, CA, USA
Conference Date: 31 January 2016
Page(s): 338 - 340
ISBN (Electronic): 978-1-4673-9467-3
ISBN (Paper): 978-1-4673-9466-6
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2016.7418045
Regular:

Phase-locked loops (PLLs) are de-facto clock generators in analog, digital, RF, and embedded systems to generate a high frequency output clock from a low frequency reference clock. Modern... View More

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