IEEE - Institute of Electrical and Electronics Engineers, Inc. - 19.7 A 65nm CMOS ADPLL with 360-¦W 1.6ps-INL SS-ADC-based period-detection-free TDC

2016 IEEE International Solid-State Circuits Conference (ISSCC)

Author(s): Akihide Sai ; Satoshi Kondo ; Tuan Thanh Ta ; Hidenori Okuni ; Masanori Furuta ; Tetsuro Itakura
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: San Francisco, CA, USA
Conference Date: 31 January 2016
Page(s): 336 - 337
ISBN (Electronic): 978-1-4673-9467-3
ISBN (Paper): 978-1-4673-9466-6
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2016.7418044
Regular:

Several research studies have considered replacing traditional analog PLLs with an all-digital PLL (ADPLL). In such studies, a key topic relates to the resolution and linearity of the TDC.... View More

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