IEEE - Institute of Electrical and Electronics Engineers, Inc. - 19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation

2016 IEEE International Solid-State Circuits Conference (ISSCC)

Author(s): Che-Wei Yeh ; Cheng-En Hsieh ; Shen-Iuan Liu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: San Francisco, CA, USA
Conference Date: 31 January 2016
Page(s): 332 - 333
ISBN (Electronic): 978-1-4673-9467-3
ISBN (Paper): 978-1-4673-9466-6
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2016.7418042
Regular:

Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring... View More

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