IEEE - Institute of Electrical and Electronics Engineers, Inc. - 19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS

2016 IEEE International Solid-State Circuits Conference (ISSCC)

Author(s): Kuan-Yueh James Shen ; Syed Feruz Syed Farooq ; Yongping Fan ; Khoa Minh Nguyen ; Qi Wang ; Amr Elshazly ; Nasser Kurd
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: San Francisco, CA, USA
Conference Date: 31 January 2016
Page(s): 330 - 331
ISBN (Electronic): 978-1-4673-9467-3
ISBN (Paper): 978-1-4673-9466-6
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2016.7418041
Regular:

With recent advancements in SoC integration, modern SoC architectures can employ more than 20 PLLs [1]. To address SoC clocking needs with an ever reducing power budget, a deep sub-mW to low-mW... View More

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