IEEE - Institute of Electrical and Electronics Engineers, Inc. - 19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS

2016 IEEE International Solid-State Circuits Conference (ISSCC)

Author(s): Hyunik Kim ; Yongjo Kim ; Taeik Kim ; Hojin Park ; SeongHwan Cho
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: San Francisco, CA, USA
Conference Date: 31 January 2016
Page(s): 328 - 329
ISBN (Electronic): 978-1-4673-9467-3
ISBN (Paper): 978-1-4673-9466-6
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2016.7418040
Regular:

A multiplying delay-locked loop (MDLL) is an attractive architecture for a low-jitter clock generator, as it does not suffer much from jitter accumulation [1-4]. By periodically replacing the... View More

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