IEEE - Institute of Electrical and Electronics Engineers, Inc. - 17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology

2016 IEEE International Solid-State Circuits Conference (ISSCC)

Author(s): John Keane ; Jaydeep Kulkarni ; Kyung-Hoae Koo ; Satyanand Nalam ; Zheng Guo ; Eric Karl ; Kevin Zhang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: San Francisco, CA, USA
Conference Date: 31 January 2016
Page(s): 308 - 309
ISBN (Electronic): 978-1-4673-9467-3
ISBN (Paper): 978-1-4673-9466-6
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2016.7418030
Regular:

System-on-Chip (SoC) designs contain a variety of IP blocks which use multiport memories to improve performance by enabling multiple simultaneous operations in the same memory bank. Conventional... View More

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