IEEE - Institute of Electrical and Electronics Engineers, Inc. - 10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface

2016 IEEE International Solid-State Circuits Conference (ISSCC)

Author(s): Wei-Han Cho ; Yilei Li ; Yuan Du ; Chien-Heng Wong ; Jieqiong Du ; Po-Tsang Huang ; Sheau Jiung Lee ; Huan-Neng Chen ; Chewn-Pu Jou ; Fu-Lung Hsueh ; Mau-Chung Frank Chang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2016
Conference Location: San Francisco, CA, USA
Conference Date: 31 January 2016
Page(s): 184 - 185
ISBN (Electronic): 978-1-4673-9467-3
ISBN (Paper): 978-1-4673-9466-6
ISSN (Electronic): 2376-8606
DOI: 10.1109/ISSCC.2016.7417968
Regular:

The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past... View More

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