IEEE - Institute of Electrical and Electronics Engineers, Inc. - Nano-CMOS circuit design and performance evaluation by inclusion of ballistic transport processes

2009 International Semiconductor Device Research Symposium (ISDRS)

Author(s): Chek, D.C.Y. ; Tan, M.L.P. ; Arora, V.K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2009
Conference Location: College Park, MD, USA, USA
Conference Date: 9 December 2009
Page(s): 1 - 2
ISBN (CD): 978-1-4244-6031-1
ISBN (Paper): 978-1-4244-6030-4
DOI: 10.1109/ISDRS.2009.5378261
Regular:

The scaling of channel length and width in a nanoscale n-type MOSFET (NMOS) and p-type MOSFET (PMOS) is examined in ballistic (B) nano-CMOS design. The ballistic process is predominant in a... View More

Advertisement