IEEE - Institute of Electrical and Electronics Engineers, Inc. - Analysis of Resistive Open Defects in a Synchronizer

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)

Author(s): Hyoung-Kook Kim ; Wen-Ben Jone ; Laung-Terng Wang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2009
Conference Location: Chicago, Illinois, USA, USA
Conference Date: 7 October 2009
Page(s): 164 - 172
ISBN (Paper): 978-0-7695-3839-6
ISSN (Paper): 1550-5774
DOI: 10.1109/DFT.2009.34
Regular:

This paper presents fault modeling and analysis for open defects in a synchronizer that is implemented by two D flip-flops. Open defects are injected into any node of the synchronizer, and HSPICE... View More

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