IEEE - Institute of Electrical and Electronics Engineers, Inc. - Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)

Author(s): Meng Zhang ; Lungu, A. ; Sorin, D.J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2009
Conference Location: Chicago, Illinois, USA, USA
Conference Date: 7 October 2009
Page(s): 277 - 285
ISBN (Paper): 978-0-7695-3839-6
ISSN (Paper): 1550-5774
DOI: 10.1109/DFT.2009.23
Regular:

Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resources in the form of... View More

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