IEEE - Institute of Electrical and Electronics Engineers, Inc. - System Level Testing via TLM 2.0 Debug Transport Interface

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT)

Author(s): Di Carlo, S. ; Hatami, N. ; Prinetto, P. ; Savino, A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2009
Conference Location: Chicago, Illinois, USA, USA
Conference Date: 7 October 2009
Page(s): 286 - 294
ISBN (Paper): 978-0-7695-3839-6
ISSN (Paper): 1550-5774
DOI: 10.1109/DFT.2009.46
Regular:

With the rapid increase in the complexity of digital circuits, the design abstraction level has to grow to face the new needs of system designers in the early phases of the design process. Along... View More

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