IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

Author(s): T. Wada ; T. Hirose ; H. Shinohara ; Y. Kawai ; K. Yuzuriha ; Y. Kohno ; S. Kayano
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 1987
Volume: 22
Page(s): 727 - 732
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/JSSC.1987.1052806
Regular:

A 128-kb word/spl times/8-b CMOS SRAM with an access time of 3 ns and a standby current of 2 /spl mu/A is described. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS... View More

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