IEEE - Institute of Electrical and Electronics Engineers, Inc. - An 86 K component bipolar VLSI masterslice with a 290-ps loaded gate delay

Author(s): M. Suzuki ; M. Hirata ; Y. Ito
Sponsor(s): IEEE Solid-State Circuits Society
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 February 1987
Volume: 22
Page(s): 41 - 46
ISSN (Paper): 0018-9200
ISSN (Online): 1558-173X
DOI: 10.1109/JSSC.1987.1052669
Regular:

A very large-scale integrated (VLSI) bipolar masterslice has been demonstrated. This masterslice has a loaded three-input ECL gate delay of 290 ps and an unloaded gate delay of 164 ps at a power... View More

Advertisement