IEEE - Institute of Electrical and Electronics Engineers, Inc. - An 8Gb/s/link, 6.5mW/Gb/s memory interface with bimodal request bus

2009 IEEE Asian Solid-State Circuits Conference (A-SSCC 2009)

Author(s): K. Chang ; Haechang Lee ; Ting Wu ; K. Kaviani ; K. Prabhu ; W. Beyene ; N. Chan ; C. Chen ; T.J. Chin ; A. Gupta ; C. Madden ; Mahabaleshwara ; L. Raghavan ; Jie Shen ; Xudong Shi
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2009
Conference Location: Taipei, Taiwan
Conference Date: 16 November 2009
Page(s): 21 - 24
ISBN (CD): 978-1-4244-4434-2
ISBN (Paper): 978-1-4244-4433-5
DOI: 10.1109/ASSCC.2009.5357237
Regular:

An 8 Gb/s/link power optimized controller memory interface is implemented in TSMC 40 nm G CMOS process. It is composed of 32 differential data links to support 32 GB/s payload. The bimodal drivers... View More

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