IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 5GHz 90-nm CMOS all digital phase-locked loop

2009 IEEE Asian Solid-State Circuits Conference (A-SSCC 2009)

Author(s): Ping Lu ; H. Sjoland
Sponsor(s): IEEE Solid-State Circuits Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2009
Conference Location: Taipei, Taiwan
Conference Date: 16 November 2009
Page(s): 65 - 68
ISBN (CD): 978-1-4244-4434-2
ISBN (Paper): 978-1-4244-4433-5
DOI: 10.1109/ASSCC.2009.5357180
Regular:

An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the... View More

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