IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video

2009 IEEE Asian Solid-State Circuits Conference (A-SSCC)

Author(s): Cheng-An Chien ; Yao-Chang Yang ; Hsiu-Cheng Chang ; Jiun-In Guo ; Jia-Wei Chen ; Jinn-Shan Wang ; Chin-Hsien Wang ; Hsiang-Hui Huang ; Ching-Hwa Cheng
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2009
Conference Location: Taipei, Taiwan, Taiwan
Conference Date: 16 November 2009
Page(s): 197 - 200
ISBN (CD): 978-1-4244-4434-2
ISBN (Paper): 978-1-4244-4433-5
DOI: 10.1109/ASSCC.2009.5357147
Regular:

The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is... View More

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