IEEE - Institute of Electrical and Electronics Engineers, Inc. - Double-gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM

2009 67th Annual Device Research Conference (DRC)

Author(s): Goel, A. ; Gupta, S. ; Bansal, A. ; Meng-Hsueh Chiang ; Roy, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2009
Conference Location: University Park, PA, USA, USA
Conference Date: 22 June 2009
Page(s): 57 - 58
ISBN (CD): 978-1-4244-3527-2
ISBN (Paper): 978-1-4244-3528-9
ISSN (CD): 1548-3770
DOI: 10.1109/DRC.2009.5354884
Regular:

Over the past few decades, CMOS technology has mainly been driven by transistor scaling. However, the scaling benefits of conventional bulk MOSFETs come at the cost of increased short channel... View More

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