IEEE - Institute of Electrical and Electronics Engineers, Inc. - Using transition test to understand timing behavior of logic circuits on UltraSPARCTM T2 family

2009 IEEE International Test Conference (ITC)

Author(s): Liang-Chi Chen ; Dickinson, P. ; Dahlgren, P. ; Davidson, S. ; Caty, O. ; Wu, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2009
Conference Location: Austin, TX, USA, USA
Conference Date: 1 November 2009
Page(s): 1 - 10
ISBN (CD): 978-1-4244-4867-8
ISBN (Paper): 978-1-4244-4868-5
ISSN (CD): 1089-3539
DOI: 10.1109/TEST.2009.5355655
Regular:

Delay test is crucial for finding slow paths and slow ICs, both during bringup and during speed binning. Path delay test has traditionally been considered to be superior in finding slow paths.... View More

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