IEEE - Institute of Electrical and Electronics Engineers, Inc. - SOI substrate readiness for 22/20 nm and for fully depleted planar device architectures

2009 IEEE International SOI Conference

Author(s): Delprat, D. ; Boedt, F. ; David, C. ; Reynaud, P. ; Alami-Idrissi, A. ; Landru, D. ; Girard, C. ; Maleville, C.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2009
Conference Location: Foster City, CA, USA, USA
Conference Date: 5 October 2009
Page(s): 1 - 4
ISBN (CD): 978-1-4244-5232-3
ISBN (Paper): 978-1-4244-4256-0
ISSN (Paper): 1078-621X
DOI: 10.1109/SOI.2009.5318744
Regular:

Fully depleted (FD) MOSFET architecture for sub-32 nm technology node requires a new SOI substrate fabrication to meet all the stringent specifications imposed by a FD device. Ultra Thin SOI... View More

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