IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimal design and performance assessment of extremely-scaled si nanowire FET on insulator

2009 IEEE International SOI Conference

Author(s): Chun-Yu Chen ; Yi-Bo Liao ; Meng-Hsueh Chiang ; Keunwoo Kim ; Wei-Chou Hsu ; Shiou-Ying Cheng
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2009
Conference Location: Foster City, CA, USA, USA
Conference Date: 5 October 2009
Page(s): 1 - 2
ISBN (CD): 978-1-4244-5232-3
ISBN (Paper): 978-1-4244-4256-0
ISSN (Paper): 1078-621X
DOI: 10.1109/SOI.2009.5318741
Regular:

Optimal design for nanowire FETs beyond 22 nm technology node is presented using numerical 3D simulation and physical analysis. Our results suggest that design optimization associated with the... View More

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