IEEE - Institute of Electrical and Electronics Engineers, Inc. - Arithmetic unit design using 180nm TSV-based 3D stacking technology

2009 IEEE International Conference on 3D System Integration (3DIC)

Author(s): Ouyang, J. ; Sun, G. ; Chen, Y. ; Duan, L. ; Zhang, T. ; Xie, Y. ; Irwin, M.J.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2009
Conference Location: San Francisco, CA, USA, USA
Conference Date: 28 September 2009
Page(s): 1 - 4
ISBN (CD): 978-1-4244-4512-7
ISBN (Paper): 978-1-4244-4511-0
DOI: 10.1109/3DIC.2009.5306565
Regular:

We describe the design of two three dimensional arithmetic units (a 3D adder and a 3D multiplier) that are implemented using through-silicon-via 3D stacking technology. Compared to their 2D... View More

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