IEEE - Institute of Electrical and Electronics Engineers, Inc. - Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks

2009 IEEE International Conference on 3D System Integration (3DIC)

Author(s): Brunschwiler, T. ; Paredes, S. ; Drechsler, U. ; Michel, B. ; Cesar, W. ; Toral, G. ; Temiz, Y. ; Leblebici, Y.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2009
Conference Location: San Francisco, CA, USA, USA
Conference Date: 28 September 2009
Page(s): 1 - 10
ISBN (CD): 978-1-4244-4512-7
ISBN (Paper): 978-1-4244-4511-0
DOI: 10.1109/3DIC.2009.5306530
Regular:

Interlayer cooling is the only heat removal concept which scales with the number of active tiers in a vertically integrated chip stack. In this work, we numerically and experimentally characterize... View More

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