IEEE - Institute of Electrical and Electronics Engineers, Inc. - System-level memory modeling for bus-based memory architecture exploration

2009 IEEE International Conference on Electro/Information Technology (eit '09)

Author(s): Zhongbo Cao ; Mercado, R. ; Rover, D.T.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 June 2009
Conference Location: Windsor, ON, Canada, Canada
Conference Date: 7 June 2009
Page(s): 239 - 244
ISBN (CD): 978-1-4244-3355-1
ISBN (Paper): 978-1-4244-3354-4
DOI: 10.1109/EIT.2009.5189619
Regular:

System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we propose a novel... View More

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