IEEE - Institute of Electrical and Electronics Engineers, Inc. - Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV)

2009 IEEE International Reliability Physics Symposium (IRPS)

Author(s): Karmarkar, A.P. ; Xiaopeng Xu ; Moroz, V.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2009
Conference Location: Montreal, QC, Canada, Canada
Conference Date: 26 April 2009
Page(s): 682 - 687
ISBN (CD): 978-1-4244-2889-2
ISBN (Paper): 978-1-4244-2888-5
ISSN (Paper): 1541-7026
DOI: 10.1109/IRPS.2009.5173329
Regular:

Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via... View More

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