IEEE - Institute of Electrical and Electronics Engineers, Inc. - Dynamic cache resizing architecture for high yield SOC

2009 IEEE International Conference on IC Design and Technology (ICICDT)

Author(s): Mohammad, B. ; Rab, M.T. ; Mohammad, K. ; Suleman, M.A.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Austin, TX, USA, USA
Conference Date: 18 May 2009
Page(s): 211 - 214
ISBN (Paper): 978-1-4244-2933-2
ISBN (Online): 978-1-4244-2934-9
DOI: 10.1109/ICICDT.2009.5166298
Regular:

Dynamic cache resizing coupled with Built In Self Test (BIST) is proposed to enhance yield of SRAM-based cache memory. BIST is used as part of the power-up sequence to identify the faulty memory... View More

Advertisement