IEEE - Institute of Electrical and Electronics Engineers, Inc. - Systematic approach of FinFET based SRAM bitcell design for 32nm node and below

2009 IEEE International Conference on IC Design and Technology (ICICDT)

Author(s): Song, S.C. ; Abu-Rahma, M. ; Han, B.M. ; Ge, L. ; Yoon, S.S. ; Wang, J. ; Yang, W. ; Liu, D. ; Hu, C. ; Yeap, G.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Austin, TX, USA, USA
Conference Date: 18 May 2009
Page(s): 165 - 168
ISBN (Paper): 978-1-4244-2933-2
ISBN (Online): 978-1-4244-2934-9
DOI: 10.1109/ICICDT.2009.5166287
Regular:

Methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves considerations on both... View More

Advertisement