IEEE - Institute of Electrical and Electronics Engineers, Inc. - Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating

2009 IEEE International Conference on IC Design and Technology (ICICDT)

Author(s): Chungki Oh ; Sangmin Kim ; Youngsoo Shin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Austin, TX, USA, USA
Conference Date: 18 May 2009
Page(s): 59 - 62
ISBN (Paper): 978-1-4244-2933-2
ISBN (Online): 978-1-4244-2934-9
DOI: 10.1109/ICICDT.2009.5166265
Regular:

Dual-edge-triggered flip-flop (DETFF) allows us to use half the clock frequency while maintaining the same throughput, thereby cutting the clock power in half. DETFF-based design, however,... View More

Advertisement