IEEE - Institute of Electrical and Electronics Engineers, Inc. - 32-bit RISC CPU Based on MIPS Instruction Fetch Module Design

2009 International Joint Conference on Artificial Intelligence (JCAI)

Author(s): Kui Yi ; Yue-Hua Ding
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2009
Conference Location: Hainan Island, China
Conference Date: 25 April 2009
Page(s): 754 - 760
ISBN (Paper): 978-0-7695-3615-6
DOI: 10.1109/JCAI.2009.158
Regular:

In this paper, we analyze MIPS instruction format, instruction data path, decoder module function and design theory basend on RISC CPUT instruction set. Furthermore, we design instruction... View More

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