IEEE - Institute of Electrical and Electronics Engineers, Inc. - Stress-enhancement technique in narrowing NMOSFETs with damascene-gate process and tensile liner

2009 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA)

Author(s): Mayuzumi, S. ; Yamakawa, S. ; Tateshita, Y. ; Tsukamoto, M. ; Wakabayashi, H. ; Ohno, T. ; Nagashima, N.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2009
Conference Location: Hsinchu, Taiwan, Taiwan
Conference Date: 27 April 2009
Page(s): 20 - 21
ISBN (CD): 978-1-4244-2785-7
ISBN (Paper): 978-1-4244-2784-0
ISSN (Paper): 1930-885X
DOI: 10.1109/VTSA.2009.5159273
Regular:

Local channel stress behaviors induced by the combination of top-cut tensile SiN stress liner and damascene-gate (gate-last) process on the channel width for nFETs are investigated by using 3D... View More

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