IEEE - Institute of Electrical and Electronics Engineers, Inc. - Hierarchical architecture for network-on-chip platform

2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Author(s): Lianq-Yu Lin ; Huang-Kai Lin ; Cheng-Yeh Wang ; Lan-Da Van ; Jing-Yang Jou
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2009
Conference Location: Hsinchu, Taiwan, Taiwan
Conference Date: 28 April 2009
Page(s): 343 - 346
ISBN (CD): 978-1-4244-2782-6
ISBN (Paper): 978-1-4244-2781-9
DOI: 10.1109/VDAT.2009.5158165
Regular:

In this paper, we propose one hierarchical 2-D mesh Network-on-Chip (NoC) platform to support applications with the complexity of several hundreds of tasks or with huge amount of transmission... View More

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