IEEE - Institute of Electrical and Electronics Engineers, Inc. - Logic synthesis for better than worst-case designs

2009 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Author(s): Cong, J. ; Minkovich, K.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2009
Conference Location: Hsinchu, Taiwan, Taiwan
Conference Date: 28 April 2009
Page(s): 166 - 169
ISBN (CD): 978-1-4244-2782-6
ISBN (Paper): 978-1-4244-2781-9
DOI: 10.1109/VDAT.2009.5158121
Regular:

In this paper we present a novel metric for measuring and optimizing the performance of circuits that operate with the clock period smaller than the worst-case delay. In particular, we developed... View More

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