IEEE - Institute of Electrical and Electronics Engineers, Inc. - Effective and Efficient Test Pattern Generation for Small Delay Defect

2009 27th IEEE VLSI Test Symposium (VTS)

Author(s): Goel, S.K. ; Devta-Prasanna, N. ; Turakhia, R.P.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Santa Cruz, CA, USA, USA
Conference Date: 3 May 2009
Page(s): 111 - 116
ISBN (Paper): 978-0-7695-3598-2
ISSN (Paper): 1093-0167
DOI: 10.1109/VTS.2009.28
Regular:

Testing for small delay defects is critical to guarantee that the manufactured silicon is timing-related defect free and to reduce quality loss associated with delay defects. Commercial solutions... View More

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