IEEE - Institute of Electrical and Electronics Engineers, Inc. - A VLSI design with built-in SRAM arrays for implementing Full Search Block Matching Algorithm

2009 IEEE 13th International Symposium on Consumer Electronics (ISCE)

Author(s): Tsung-Yi Wu ; Kuang-Yao Chen ; Shi-Yi Huang ; Tai-Lun Li ; How-Rern Lin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Kyoto, Japan, Japan
Conference Date: 25 May 2009
Page(s): 619 - 621
ISBN (CD): 978-1-4244-2976-9
ISBN (Paper): 978-1-4244-2975-2
DOI: 10.1109/ISCE.2009.5156949
Regular:

A conventional 2-dimensional (2-D) systolic processing element (PE) array of a chip used for implementing Full Search Block Matching Algorithm (FSBMA) needs a large number of input pads to read... View More

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