IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor

2009 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

Author(s): Taecheol Oh ; Hyunjin Lee ; Kiyeon Lee ; Sangyeun Cho
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Tampa, Florida, USA, USA
Conference Date: 13 May 2009
Page(s): 181 - 186
ISBN (CD): 978-0-7695-3684-2
ISBN (Paper): 978-1-4244-4408-3
DOI: 10.1109/ISVLSI.2009.27
Regular:

A key design issue for chip multiprocessors (CMPs) is how to exploit the finite chip area to get the best system throughput.The most dominant area-consuming components in a CMP are processor cores... View More

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