IEEE - Institute of Electrical and Electronics Engineers, Inc. - Buffer planning for 3D ICs

2009 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): Sheqin Dong ; Hongjie Bai ; Xianlong Hong ; S. Goto
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Taipei, Taiwan
Conference Date: 24 May 2009
Page(s): 1,735 - 1,738
ISBN (CD): 978-1-4244-3828-0
ISBN (Paper): 978-1-4244-3827-3
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2009.5118110
Regular:

With recent advance of VLSI design, interconnect delay plays dominant role in the chip performance. 3D integration, which stacks multiple device layers, greatly reduces interconnect delay. Buffer... View More

Advertisement