IEEE - Institute of Electrical and Electronics Engineers, Inc. - Throughput maximization for wave-pipelined interconnects using cascaded buffers and transistor sizing

2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

Author(s): Li Wang ; T. Mak ; P. Sedcole ; P.Y.K. Cheung
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Taipei, Taiwan
Conference Date: 24 May 2009
Page(s): 1,293 - 1,296
ISBN (CD): 978-1-4244-3828-0
ISBN (Paper): 978-1-4244-3827-3
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2009.5118000
Regular:

This paper presents two new design methodologies for throughput-centric wave-pipelined interconnects: cascaded buffers insertion and transistor sizing. Experimental results show that up to 185%... View More

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