IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimization of wire grid size for differential routing and impact on the power-delay-area tradeoff

2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

Author(s): M. Alioto ; S. Badel ; Y. Leblebici
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Taipei, Taiwan
Conference Date: 24 May 2009
Page(s): 1,285 - 1,288
ISBN (CD): 978-1-4244-3828-0
ISBN (Paper): 978-1-4244-3827-3
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2009.5117998
Regular:

In this paper, the impact of the wire grid size on the power-delay-area tradeoff of VLSI digital circuits with differential routing is analyzed. To this aim, the differential MOS current-mode... View More

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