IEEE - Institute of Electrical and Electronics Engineers, Inc. - Time-multiplexed data flow graph for the design of configurable multiplier block

2009 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): Jiajia Chen ; Chip-Hong Chang ; Ching-Chuen Jong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Taipei, Taiwan
Conference Date: 24 May 2009
Page(s): 1,145 - 1,148
ISBN (CD): 978-1-4244-3828-0
ISBN (Paper): 978-1-4244-3827-3
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2009.5117963
Regular:

This paper proposes a new design methodology to reduce the logic complexity of reconfigurable multiplier block (ReMB). The minimization problem is modeled as a scheduled time-multiplexed data flow... View More

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