IEEE - Institute of Electrical and Electronics Engineers, Inc. - A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors

2009 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): A.T. Tran ; D.N. Truong ; B.M. Baas
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Taipei, Taiwan
Conference Date: 24 May 2009
Page(s): 996 - 999
ISBN (CD): 978-1-4244-3828-0
ISBN (Paper): 978-1-4244-3827-3
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2009.5117926
Regular:

The globally asynchronous locally synchronous (GALS) design style for a large area chip has become increasingly attractive due to the difficulty of designing global clocking circuits at high clock... View More

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