IEEE - Institute of Electrical and Electronics Engineers, Inc. - A time-interleaved flash-SAR architecture for high speed A/D conversion

2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009

Author(s): Ba Sung ; Sang-Hyun Cho ; Chang-Kyo Lee ; Jong-In Kim ; Seung-Tak Ryu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Taipei, Taiwan
Conference Date: 24 May 2009
Page(s): 984 - 987
ISBN (CD): 978-1-4244-3828-0
ISBN (Paper): 978-1-4244-3827-3
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2009.5117923
Regular:

A time-interleaved flash-SAR ADC architecture has been suggested for high speed A/D conversion. Owing to the MSBs determined by the front end flash ADC, SAR ADC completes the A/D conversion in a... View More

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