IEEE - Institute of Electrical and Electronics Engineers, Inc. - An energy-efficient dual sampling SAR ADC with reduced capacitive DAC

2009 IEEE International Symposium on Circuits and Systems (ISCAS)

Author(s): Binhee Kim ; Long Yan ; J. Yoo ; Namjun Cho ; Hoi-Jun Yoo
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Taipei, Taiwan
Conference Date: 24 May 2009
Page(s): 972 - 975
ISBN (CD): 978-1-4244-3828-0
ISBN (Paper): 978-1-4244-3827-3
ISSN (Electronic): 2158-1525
ISSN (Paper): 0271-4302
DOI: 10.1109/ISCAS.2009.5117920
Regular:

This paper presents an energy-efficient SAR ADC which adopts reduced MSB cycling step with dual sampling of the analog signal. By sampling and holding the analog signal asymmetrically at both... View More

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