IEEE - Institute of Electrical and Electronics Engineers, Inc. - Performance-constrained parasitic-aware retargeting and optimization of analog layouts

2009 Canadian Conference on Electrical and Computer Engineering (CCECE)

Author(s): Zheng Liu ; Lihong Zhang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: St. John's, NL, Canada, Canada
Conference Date: 3 May 2009
Page(s): 1,194 - 1,197
ISBN (CD): 978-1-4244-3508-1
ISBN (Paper): 978-1-4244-3509-8
ISSN (Paper): 0840-7789
DOI: 10.1109/CCECE.2009.5090314
Regular:

Performance of analog circuits is highly sensitive to layout parasitics. This paper presents an improved algorithm that automatically conducts performance-constrained parasitic-aware... View More

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