IEEE - Institute of Electrical and Electronics Engineers, Inc. - JEDEC board drop test simulation for wafer level packages (WLPs)

2009 IEEE 59th Electronic Components and Technology Conference (ECTC 2009)

Author(s): Dhiman, H.S. ; Xuejun Fan ; Tiao Zhou
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: San Diego, CA, USA, USA
Conference Date: 26 May 2009
Page(s): 556 - 564
ISBN (CD): 978-1-4244-4476-2
ISBN (Paper): 978-1-4244-4475-5
ISSN (Paper): 0569-5503
DOI: 10.1109/ECTC.2009.5074068
Regular:

In this paper, a comprehensive study is carried out to investigate the WLP package dynamic behaviors subjected to drop impact according to the JEDEC specification. First, a Direct Acceleration... View More

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