IEEE - Institute of Electrical and Electronics Engineers, Inc. - Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

2009 39th International Symposium on Multiple-Valued Logic (ISMVL)

Author(s): Melis, W.J.C. ; Chizuwa, S. ; Kameyama, M.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 May 2009
Conference Location: Naha, Okinawaw, Japan, Japan
Conference Date: 21 May 2009
Page(s): 233 - 238
ISBN (CD): 978-0-7695-3607-1
ISBN (Paper): 978-1-4244-3841-9
ISSN (Paper): 0195-623X
DOI: 10.1109/ISMVL.2009.11
Regular:

A large number of real world applications, like user support systems, can still not be performed easily by conventional algorithms in comparison with the human brain. Recently, such intelligence... View More

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