IEEE - Institute of Electrical and Electronics Engineers, Inc. - Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

2009 IEEE 15th International Symposium on High Performance Computer Architecture (HPCA)

Author(s): Madan, N. ; Li Zhao ; Muralimanohar, N. ; Udipi, A. ; Balasubramonian, R. ; Iyer, R. ; Makineni, S. ; Newell, D.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 February 2009
Conference Location: Raleigh, NC, USA, USA
Conference Date: 14 February 2009
Page(s): 262 - 274
ISBN (Paper): 978-1-4244-2932-5
ISSN (Paper): 1530-0897
DOI: 10.1109/HPCA.2009.4798261
Regular:

Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postulate a 3D chip... View More

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