IEEE - Institute of Electrical and Electronics Engineers, Inc. - Memory subsystem simulation in software TLM/T models

2009 Asia and South Pacific Design Automation Conference (ASP-DAC)

Author(s): Cheung, E. ; Hsieh, H. ; Balarin, F.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2009
Conference Location: Yokohama, Japan, Japan
Conference Date: 19 January 2009
Page(s): 811 - 816
ISBN (CD): 978-1-4244-2749-9
ISBN (Paper): 978-1-4244-2748-2
DOI: 10.1109/ASPDAC.2009.4796580
Regular:

Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since thememory subsystemaccounts for up to 50%of the performance and energy expenditures,... View More

Advertisement