IEEE - Institute of Electrical and Electronics Engineers, Inc. - Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model

2009 Asia and South Pacific Design Automation Conference (ASP-DAC)

Author(s): Chen Kang Lo ; Ren Song Tsay
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2009
Conference Location: Yokohama, Japan, Japan
Conference Date: 19 January 2009
Page(s): 558 - 563
ISBN (CD): 978-1-4244-2749-9
ISBN (Paper): 978-1-4244-2748-2
DOI: 10.1109/ASPDAC.2009.4796539
Regular:

This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level Modeling) is proven... View More

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