IEEE - Institute of Electrical and Electronics Engineers, Inc. - Partial order method for timed simulation of system-level MPSoC designs

2009 Asia and South Pacific Design Automation Conference (ASP-DAC)

Author(s): Cheung, E. ; Hsieh, H. ; Balarin, F.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2009
Conference Location: Yokohama, Japan, Japan
Conference Date: 19 January 2009
Page(s): 149 - 154
ISBN (CD): 978-1-4244-2749-9
ISBN (Paper): 978-1-4244-2748-2
DOI: 10.1109/ASPDAC.2009.4796472
Regular:

Current discrete event simulator requires heavy simulation overhead to switch between different components to simulate them in strictly chronological order. Therefore, timed simulation is... View More

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